Parallel Processing MCQs

Multiple Choice Questions 17 Pages

Mahatma Gandhi University

BSc Computer Science

JAK

Contributed by

Jagat Aslam Khan

MAHATMA GANDHI UNIVERSITY
SCHOOL OF DISTANCE EDUCATION
(MGU – CBCSS – UG – SDE 2012)

B.Sc Computer Science
Semester V
BCS 601 Core -24 : Parallel Processing
Multiple Choice questions

1. A collection of lines that connects several devices is called ..............
A. bus
B. peripheral connection wires
C. Both a and b
D. internal wires
2. A complete microcomputer system consist of ...........
A. microprocessor
B. memory
C. peripheral equipment
D. all of the above
3. PC Program Counter is also called ...................
A. instruction pointer
B. memory pointer
C. data counter
D. file pointer
4. In a single byte how many bits will be there?
A. 8
B. 16
C. 4
D. 32
5. CPU does not perform the operation ..................
A. data transfer
B. logic operation
C. arithmetic operation
D. all of the above
6. The access time of memory is ............... the time required for performing any single CPU
operation.
A. Longer than
B. Shorter than
C. Negligible than
D. Same as
7. Memory address refers to the successive memory words and the machine is called as ............
A. word addressable
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B. byte addressable
C. bit addressable
D. Terra byte addressable

8. A microprogram written as string of 0's and 1's is a .............
A. Symbolic microinstruction
B. binary microinstruction
C. symbolic microinstruction
D. binary micro-program

9. A pipeline is like ....................
A. an automobile assembly line
B. house pipeline
C. both a and b
D. a gas line

10. Data hazards occur when .....................
A. Greater performance loss
B. Pipeline changes the order of read/write access to operands
C. Some functional unit is not fully pipelined
D. Machine size is limited

11. Processors of all computers, whether micro, mini or mainframe must have
A. ALU
B. Primary Storage
C. Control unit
D. All of above

12. What is the control unit's function in the CPU?
A. To transfer data to primary storage
B. to store program instruction
C. to perform logic operations
D. to decode program instruction

13. What is meant by a dedicated computer?
A. which is used by one person only
B. which is assigned to one and only one task
C. which does one kind of software
D. which is meant for application software only

14. The most common addressing techiniques employed by a CPU is
A. immediate
B. direct
C. indirect
D. register
E. all of the above

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15. Pipeline implement
A. fetch instruction
B. decode instruction
C. fetch operand
D. calculate operand
E. execute instruction
F. all of abve

16. Which of the following code is used in present day computing was developed by IBM
corporation?
A. ASCII
B. Hollerith Code
C. Baudot code
D. EBCDIC code

17. When a subroutine is called, the address of the instruction following the CALL instructions
stored in/on the
A. stack pointer
B. accumulator
C. program counter
D. Stack

18. A microprogram written as string of 0's and 1's is a
A. symbolic microinstruction
B. binary microinstruction
C. symbolic microprogram
D. binary microprogram

19. Interrupts which are initiated by an instruction are
A. internal
B. external
C. hardware
D. Software

20. Memory access in RISC architecture is limited to instructions
A. CALL and RET
B. PUSH and POP
C. STA and LDA
D. MOV and JMP

21. From where interrupts are generated?
A)Central processing unit
B) Memory chips
C) Registers
D) I/O devices

22. The output of a gate is low when at least one of its input is low . It is true for
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A)AND gate
B) OR gate
C) NAND gate
D) NOR gate

23. Which one of the following is most suitable to make a parity checker
A) AND gate
B) OR gate
C) Exclusive- OR gate
D) None of the above

24What is the minimum number of flip-flops required in a counter to count 100 pulses?
A)Five
B) seven
C) Ten
D) hundred

25. For a RS flip-flop constructed with NAND gates and input R=1 and s=1 the state is
A) Memory state
B) Set state
C) Reset state
D) Unused state

26. The advantage of RISC processor over CISC processor is that
A) The hardware architecture is simpler
B) An instruction can be executed in one cycle
C) Less number of registers accommodate in chip
D) Parallel execution capabilities

27. Which of the following is true about interrupts?
A) They are generated when memory cycles are stolen
B) They are used in place of data channels
C) They can be generated by arithmetic operation
D) They can indicate completion of an I/O operation

28. Te devices connected to a microprocessor can use the data bus:
A) all the time
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B) at regular interval of time
C) only when it’s sending or receiving data
D) when the microprocessor is reset

29. Intel 8080 microprocessor has an instruction set of 91 instruction . The opcode to implement
this instruction set should be at least
A) 3 bit long
B) 5 bit long
C) 7 bit long
D) 9 bit long

30. Dynamic RAMs are best suited to
A) slow system
B) large system
C) one bit system
D) none of the above

31. Intel Pentium CPU is a
A. RISC based
B. CISC based
C. Both of the above
D. None of the above
32. A modem is used to link up two computers via
A. telephone line
B. dedicated line
C. Both of the above
D. None of the above
33. The maximum integer which can be stored on a 8 bit accumulator is
A. 112
B. 200
C. 255
D. 224
34. In a system with a 16 bit address bus, what is the maximum number of 1K byte memory devices
it could contain
A. 16
B. 64
C. 256
D. 65536
35. Which of the following memories in a computer is volatile?
A. RAM
B. ROM
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C. EPROM
D. ALL
36. A peripheral is
A. any drives installed in the computer
B. tapedrive connected to a computer
C. any physical device connected to the computer
D. None of above
37. How many bits do you think will be adequate to encode individual character in Devnagari script
A. 12
B. 16
C. 64
D. 10
38. Which of the following bus is used to transfer data from main memory to peripheral device?
A. DMA bus
B. Output bus
C. Data bus
D.All of the above
39. To provide increased memory capacity for operating system, the
A. virtual memory is created
B. cache memory is increased
C. memory for OS is reserved
D. Additional memory is installed
40. CD -RAW is
A. Input device only
B. output device only
C. Both of the above
D. None of the above

41. Which of the following require large computer memory?
A. Imaging
B. Graphics
C. Voice
D. All of the above
42. Which major development led to the production of microcomputers?
A. Magnetic disks
B. floppy disks
C. Logic gates
D. Integrated Circuits
43. In immediate addressing the operand is placed
A. in the CPU register
B. after opcode in the instruction
C. in the memory
D. in the stack
44. Micro instructions are stored in
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A. computer memory
B. primary storage
C. secondary storage
D. control memory
E. cache memory
45. Pipeline processing implement
A. fetch instruction
B. decode instruction
C. fetch operand
D. calculate operand
E. execute instruction
F. all of the above
46. The 16- bit registers in 8085 is
A. general purpose register
B. accumulator
C. stack pointer and program counter
D. all of the above
47. Instruction pipelining has minimum stages
A. 4
B. 2
C. 3
D. 6
48. Systems that do not have parallel processing capabilities are
A. SISD
B. SIMD
C. MIMD
D. All of the above
49. The word size of the microprocessor refers to
A. the amount of a information that can be stored in a byte
B. the amount of a information that can be stored in a cycle **
C. The number of machine operations performed in a second
D. the maximum length of an English word that can be input to a computer
50. How many address lines are needed to address each memory location in a 2048X 4 memory
chip?
A. 10
B. 11
C. 8
D. 12

51. Who is regarded as the founder of Computer Architecture?
A. Alan Turing
B. Konrad Zuse
C. John von Neumann
D. John William Mauchly
E. None of the answers above is correct

52. What is characteristic for the organization of a computer
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architecture?
A. Size
B. Dynamic behaviour
C. Static behaviour
D. Speed
E. None of the answers above is correct
53. What is usually regarded as the von Neumann Bottleneck?
A. Processor/memory interface
B. Control unit
C. Arithmetic logical unit
D. Instruction set
E. None of the answers above is correct
54. How does the number of transistors per chip increase
according to Moore s law?
A. Quadratically
B. Linearly
C. Cubicly
D. Exponentially
E. None of the answers above is correct
55. Who is regarded as the founder of Computer Science?
A. Alan Turing
B. Konrad Zuse
C. J. Presper Eckert
D. John William Mauchly
E. None of the answers above is correct
56. Which is the fastest storage unit in a usual memory
hierarchy?
A. Cache
B. Main memory
C. Hard disk
D. Register
E. None of the answers above is correct
57. Which cache miss does not occur in case of a fully associative cache?
A. Conflict miss
B. Capacity miss
C. Compulsory miss
D. Cold start miss
E. None of the answers above is correct
58. Which miss even occurs in infinite caches?
A. Coherence miss
B. Capacity miss
C. Conflict miss
D. Cold start miss
E. None of the answers above is correct
59. What is stored in a Translation Lookaside Buffer?
A. System dumps
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B. Physical addresses
C. rogram data
D. Operating system log files
E. None of the answers above is correct
50. Which value has the speedup of a parallel program that
achieves an efficiency of 75% on 32 processors?
A. 18
B. 24
C. 16
D. 20
E. None of the answers above is correct

61. Pipelining strategy is called implement
[A] instruction execution
[B] instruction prefetch
[C] instruction decoding
[D] instruction manipulation

62. The concept of pipelining is most effective in improving performance if the tasks being
performed in different stages :
[A] require different amount of time
[B] require about the same amount of time
[C] require different amount of time with time difference between any two tasks being same
[D] require different amount with time difference between any two tasks being different

63. Which Algorithm is better choice for pipelining?
[A] Small Algorithm
[B] Hash Algorithm
[C] Merge-Sort Algorithm [
[D] Quick-Sort Algorithm

64. The expression 'delayed load' is used in context of
[A] processor-printer communication
[B] memory-monitor communication
[C] pipelining
[D] none of the above

65. Parallel processing may occur
[A] in the instruction stream
[B] in the data stream
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[C] both[A] and [B]
[D] none of the above

66. The cost of a parallel processing is primarily determined by :
[A] Time Complexity
[B] Switching Complexity
[C] Circuit Complexity
[D] None of the above

67. An instruction to provide small delay in program
[A] LDA
[B] NOP
[C] BEA
[D] None of the above

68. Characteristic of RISC (Reduced Instruction Set Computer) instruction set is
[A] three instructions per cycle
[B] two instructions per cycle
[C] one instruction per cycle
[D] none of the

69. In daisy-chaining priority method, all the devices that can request an interrupt are connected in
[A] parallel
[B] serial
[C] random
[D] none of the above

70. Which one of the following is a characteristic of CISC (Complex Instruction Set Computer) [A]
Fixed format instructions
[B] Variable format instructions
[C] Instructions are executed by hardware
[D] None of the above

71. During the execution of the instructions, a copy of the instructions is placed in the
______ .
A. Register
B. RAM
C. System heap
D. Cache

72. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose
A can execute an instruction with an average of 3 steps and B can execute with an average of 5
steps. For the execution of the same instruction which processor is faster ?
A. A
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Parallel Processing MCQs

Parallel Processing MCQs

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