ADE (UNIT-II) MCQs

Multiple Choice Questions 36 Pages

Savitribai Phule Pune University

electrical engineering

GUC

Contributed by

Gowri Umesh Chatterjee

SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
2
((QUESTION))
Determine the output frequency for a frequency division circuit that
contains 12 flip-flops with an input clock frequency of 20.48 MHz
((OPTION_A))
10.24 kHz

((OPTION_B))
5 kHz

((OPTION_C))
30.24 kHz

((OPTION_D))
15 kHz
((CORRECT_C
HOICE))
(A/B/C/D)
B
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
1
((QUESTION))
Which statement BEST describes the operation of a negative-edge-
triggered D flip-flop?
((OPTION_A))
The logic level at the D input is transferred to Q on NGT of CLK.

((OPTION_B))
The Q output is ALWAYS identical to the CLK input if the D input is
HIGH.

((OPTION_C))
The Q output is ALWAYS identical to the D input when CLK = PGT.

((OPTION_D))
The Q output is ALWAYS identical to the D input.
((CORRECT_C
HOICE))
(A/B/C/D)
A
((EXPLANATI
ON))
(OPTIONAL)

Page 1
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
2
((QUESTION))
Propagation delay time, t
PLH
, is measured from the ________.
((OPTION_A))
triggering edge of the clock pulse to the LOW-to-HIGH transition of the
output

((OPTION_B))
triggering edge of the clock pulse to the HIGH-to-LOW transition of the
output

((OPTION_C))
preset input to the LOW-to-HIGH transition of the output
((OPTION_D))
clear input to the HIGH-to-LOW transition of the output

((CORRECT_C
HOICE))
(A/B/C/D)
A
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
1
((QUESTION))
How is a J-K flip-flop made to toggle?
((OPTION_A))
J = 0, K = 0

((OPTION_B))
J = 1, K = 0

((OPTION_C))
J = 0, K = 1

((OPTION_D))
J = 1, K = 1
((CORRECT_C
HOICE))
(A/B/C/D)
D
((EXPLANATI
ON))
(OPTIONAL)

Page 2
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
1
((QUESTION))
How many flip-flops are in the 7475 IC?
((OPTION_A))
1
((OPTION_B))
2
((OPTION_C))
4
((OPTION_D))
8
((CORRECT_C
HOICE))
(A/B/C/D)
C
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
2
((QUESTION))
How many flip-flops are required to produce a divide-by-128 device?
((OPTION_A))
1
((OPTION_B))
4
((OPTION_C))
6
((OPTION_D))
7
((CORRECT_C
HOICE))
(A/B/C/D)
D
((EXPLANATI
ON))
(OPTIONAL)

Page 3
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
2
((QUESTION))
The phenomenon of interpreting unwanted signals on J and K while C
p

(clock pulse) is HIGH is called ________.
((OPTION_A))
parity error checking

((OPTION_B))
ones catching

((OPTION_C))
digital discrimination

((OPTION_D))
digital filtering
((CORRECT_C
HOICE))
(A/B/C/D)
B
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
1
((QUESTION))
What is another name for a one-shot?
((OPTION_A))
Monostable
((OPTION_B))
Multivibrator
((OPTION_C))
Bistable
((OPTION_D))
Astable
((CORRECT_C
HOICE))
(A/B/C/D)
A
((EXPLANATI
ON))
(OPTIONAL)

Page 4
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
1
((QUESTION))
On a master-slave flip-flop, when is the master enabled
((OPTION_A))
when the gate is LOW

((OPTION_B))
when the gate is HIGH

((OPTION_C))
both of the above

((OPTION_D))
neither of the above
((CORRECT_C
HOICE))
(A/B/C/D)
B
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
1
((QUESTION))
One example of the use of an S-R flip-flop is as a(n):
((OPTION_A))
racer

((OPTION_B))
astable oscillator

((OPTION_C))
binary storage register

((OPTION_D))
transition pulse generator
((CORRECT_C
HOICE))
(A/B/C/D)
C
((EXPLANATI
ON))
(OPTIONAL)

Page 5
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
1
((QUESTION))
What is the difference between the 7476 and the 74LS76?
((OPTION_A))
the 7476 is master-slave, the 74LS76 is master-slave

((OPTION_B))
the 7476 is edge-triggered, the 74LS76 is edge-triggered

((OPTION_C))
the 7476 is edge-triggered, the 74LS76 is master-slave

((OPTION_D))
the 7476 is master-slave, the 74LS76 is edge-triggered
((CORRECT_C
HOICE))
(A/B/C/D)
D
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
2
((QUESTION))
Which of the following is correct for a gated D flip-flop?
((OPTION_A))
The output toggles if one of the inputs is held HIGH.

((OPTION_B))
Only one of the inputs can be HIGH at a time.

((OPTION_C))
The output complement follows the input when enabled.

((OPTION_D))
Q output follows the input D when the enable is HIGH.
((CORRECT_C
HOICE))
(A/B/C/D)
D
((EXPLANATI
ON))
(OPTIONAL)

Page 6
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
1
((QUESTION))
With regard to a D latch, ________.
((OPTION_A))
the Q output follows the D input when EN is LOW

((OPTION_B))
the Q output is opposite the D input when EN is LOW

((OPTION_C))
the Q output follows the D input when EN is HIGH

((OPTION_D))
the Q output is HIGH regardless of EN's input state

((CORRECT_C
HOICE))
(A/B/C/D)
C
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
2
((QUESTION))
How can the cross-coupled NAND flip-flop be made to have active-HIGH
S-R inputs?
((OPTION_A))
It can't be done.

((OPTION_B))
Invert the Q outputs.

((OPTION_C))
Invert the S-R inputs.
((OPTION_D))
Invert only R.
((CORRECT_C
HOICE))
(A/B/C/D)
C
((EXPLANATI
ON))
(OPTIONAL)

Page 7
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
1
((QUESTION))
When is a flip-flop said to be transparent?
((OPTION_A))
when the Q output is opposite the input

((OPTION_B))
when the Q output follows the input

((OPTION_C))
when you can see through the IC packaging
((OPTION_D))
Not possible.
((CORRECT_C
HOICE))
(A/B/C/D)
B
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
1
((QUESTION))
Which of the following is correct for a D latch?
((OPTION_A))
The output toggles if one of the inputs is held HIGH.
((OPTION_B))
Q output follows the input D when the enable is HIGH.
((OPTION_C))
Only one of the inputs can be HIGH at a time.
((OPTION_D))
The output complement follows the input when enabled.
((CORRECT_C
HOICE))
(A/B/C/D)
B
((EXPLANATI
ON))
(OPTIONAL)

Page 8
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
1
((QUESTION))
A J-K flip-flop is in a "no change" condition when ________.
((OPTION_A))
J = 1, K = 1
((OPTION_B))
J = 1, K = 0
((OPTION_C))
J = 0, K = 1
((OPTION_D))
J = 0, K = 0
((CORRECT_C
HOICE))
(A/B/C/D)
D
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
1
((QUESTION))
A correct output is achieved from a master-slave J-K flip-flop only if its
inputs are stable while the:
((OPTION_A))
clock is LOW
((OPTION_B))
slave is transferring
((OPTION_C))
flip-flop is reset
((OPTION_D))
clock is HIGH
((CORRECT_C
HOICE))
(A/B/C/D)
D
((EXPLANATI
ON))
(OPTIONAL)

Page 9
SKN SITS, LONAVALA
DEPARTMENT OF ELECTRICAL ENGINEERING
S.E. Electrical Subject:- ADE (UNIT-II)

((MARKS))
(1/2/3...)
1
((QUESTION))
Which of the following describes the operation of a positive edge-triggered D
flip-flop?
((OPTION_A))
If both inputs are HIGH, the output will toggle.
((OPTION_B))
The output will follow the input on the leading edge of the clock.
((OPTION_C))
When both inputs are LOW, an invalid state exists.
((OPTION_D))
The input is toggled into the flip-flop on the leading edge of the clock and
is passed to the output on the trailing edge of the clock.
((CORRECT_C
HOICE))
(A/B/C/D)
B
((EXPLANATI
ON))
(OPTIONAL)

((MARKS))
(1/2/3...)
1
((QUESTION))
What is the hold condition of a flip-flop?
((OPTION_A))
both S and R inputs activated
((OPTION_B))
no active S or R input
((OPTION_C))
only S is active
((OPTION_D))
only R is active
((CORRECT_C
HOICE))
(A/B/C/D)
B
((EXPLANATI
ON))
(OPTIONAL)

Page 10

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